Processor information (cpu info):
cat /proc/cpuinfo
CPU count:
wc -l /proc/net/softnet_stat
Features: swp half thumb fastmult edsp
/bin/dmesg | grep 'ARM'

http://unix.stackexchange.com/questions/43539/what-do-the-flags-in-proc-cpuinfo-mean

gcc -march=native -mtune=native -Q -O2 --help=target

http://www.oracle.com/technetwork/java/embedded/embedded-se/downloads/javase-embedded-downloads-2209751.html
ARMv5 Linux – Headless EABI, SoftFP ABI, Little Endian3
The Marvell® 88F6281 SoC with Sheeva™ embedded CPU technology, is a high-performance integrated controller. It
integrates the Marvell Sheeva CPU core which is fully ARMv5TE-compliant with a 256KB L2 Cache. The 88F6281 builds
upon Marvell’s innovative Feroceon® family of processors, improves performance, and adds new features to reduce bill of
materials (BOM) costs. The 88F6281 is suitable for a wide range of applications such as routers, gateway, media server,
storage, set-top-box, networking, point of service and printer products.
Marvell Kirkwood 88F6281 (SheevaPlug) (Sheeva 88SV131 CPU core) (Feroceon 88FR131 rev 1 (v5l)) 1200 MHz

Conform http://comments.gmane.org/gmane.linux.ports.arm.kernel/50421:
-mtune=marvell-f sau -mtune=xscale

Product Brief
http://www.marvell.com/embedded-processors/kirkwood/assets/88F6281-004_ver1.pdf
Hardware Spec:
http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F6281_OpenSource.pdf
Functional Spec:
http://www.marvell.com/embedded-processors/kirkwood/assets/88F6281-004_ver1.pdf

Architecture version:
http://www.altera.com/literature/third-party/archives/ddi0100e_arm_arm.pdf

armv5te: 
	ARM instruction set version = 5
	thumb instruction set version = 2
	long multiply instruction = yes
	enchanced DSP instruction = yes